(1) Field of the Invention
The present invention relates in general to the fabrication of semiconductor devices for integrated circuits, and more particularly to a method for forming a modified field oxide (FOX) isolation that increases the field oxide threshold voltages (Vth), for a specific channel-stop implant dose under the FOX. Alternatively, the Vth can be maintained at a constant value while the channel-stop implant dose can be reduced, which results in lower leakage currents between device areas. The method is particularly useful for dynamic random access memory (DRAM) for decreasing leakage currents and thereby increasing the refresh cycle times for storage capacitors.
(2) Description of the Prior Art
In the fabrication of semiconductor circuits, field oxide regions are formed in and on the silicon substrate (wafer) to surround and electrically isolate the device areas. One of the most common and cost-effective methods of forming this field oxide isolation in the semiconductor industry is by the LOCal Oxidation of Silicon (LOCOS) technique.
The LOCOS technique involves growing a pad oxide on the silicon substrate as a stress-release layer. A silicon nitride (Si3N4) layer that is a barrier layer to oxidation is deposited, typically by chemical vapor deposition (CVD). Conventional photolithographic techniques and plasma etching are then used to pattern the silicon nitride layer, leaving portions of the silicon nitride over the required device areas while exposing the silicon substrate in areas where the field oxide (FOX) isolation is required. By conventional methods, with the photoresist mask still in place, a P dopant (boron) is implanted in the field oxide areas to form channel-stop regions. The channel-stop regions prevent surface depletion or inversion at the field oxide/silicon substrate interface after the field oxide is formed by LOCOS, and prevent parasitic field oxide MOSFETs from turning on when the chip is powered up. The substrate is then subjected to a thermal oxidation to form the silicon oxide field oxide isolation regions having the channel-stop implants underneath. However, because of the high segregation coefficient for boron into the field oxide during the relatively long LOCOS oxidation cycle, higher implant doses are used to prevent inversion. Alternatively, to avoid the segregation, another method is to implant the boron ions through the field oxide after the LOCOS oxide is grown.
However, the LOCOS method, even with implanting through the field oxide, has several problems as the device feature sizes decrease and the circuit density increases. One problem is the lateral oxidation of the silicon substrate under the silicon nitride mask forming what are commonly referred to in the industry as xe2x80x9cbirds"" beaks.xe2x80x9d These birds"" beaks extend into and reduce the active device areas and are much thinner than the LOCOS FOX that is grown in the regions between the patterned Si3N4 layers. Also, as the width of the LOCOS between adjacent device areas decreases, the channel-stop implant through the field oxide becomes less effective, especially under the bird""s beaks, and therefore requires a higher implant dose. However, this results in higher leakage currents that shorten the refresh cycle time and reduce the DRAM performance.
One method of reducing the bird""s beak is by using a polysilicon buffer LOCOS, referred to as PBLOCOS. Another method for reducing the bird""s beak is the use of a double silicon nitride layer and a polysilicon layer as described by Chen in U.S. Pat. No. 5,397,732. Another method for forming a planar field oxide without birds"" beaks is described by Philipossian et al. in U.S. Pat. No. 5,316,965 but requires etching trenches in the silicon substrate in which the recessed trench isolation is fabricated. Typically these methods require more complex processing than the more conventional LOCOS technique.
However, one problem that arises when narrow field oxide regions are formed by the more conventional LOCOS method is that the birds"" beaks formed under the silicon nitride layer are thinner than the main field oxide region and can result in lower field oxide parasitic threshold voltages (Vth) because of the deeper channel-stop region when the field implant is implanted through the birds"" beaks. One method is to increase the implant dose, but this leads to increased junction leakage and would degrade circuit performance, such as on DRAMs.
However, there is still a need to improve upon the more conventional LOCOS process while maintaining narrow FOX regions with increased FOX threshold voltages (Vth) and minimizing the leakage current between adjacent device areas.
It is a principal object of this invention to provide a field oxide isolation region having higher threshold voltages and reduced leakage currents between adjacent device areas.
It is another object of this invention to provide these higher threshold voltages and reduced leakage currents by forming additional insulating sidewall portions along the perimeter of the field oxide regions which modify the channel-stop implant profile when the channel-stop implant dopant is implanted through the modified field oxide.
It is an object of this invention to provide a new structure and method for forming field oxide isolation regions by providing a modified LOCOS structure. The method consists of depositing a conformal insulating layer over the more conventional LOCOS field oxide, and anisotropically plasma etching back to form a thicker insulation over the perimeter of the LOCOS field oxide, commonly referred to as the xe2x80x9cbird""s beakxe2x80x9d. This modifies the profile of the channel-stop implant through the field oxide which provides a more robust isolation having increased field oxide threshold voltages (Vth) and reduced leakage currents.
In summary, the method of forming the field isolation structure begins by providing a semiconductor substrate, such as a single-crystal silicon. A silicon oxide layer is formed on the surface of the silicon substrate to provide a stress-release pad oxide layer. A silicon nitride layer is deposited on the pad oxide layer, which provides an oxidation barrier layer. The silicon nitride layer and the pad oxide layer are patterned to leave portions over the device areas, while providing openings over the areas surrounding the device areas where the field oxide isolation regions are required. The silicon substrate is then thermally oxidized in the openings, while the silicon nitride layer prevents oxidation of the device areas, thereby forming a field oxide that by the LOCOS method results in thinner portions, commonly referred to as xe2x80x9cbird""s beakxe2x80x9d on the perimeter of the field oxide extending under the silicon nitride layer. The silicon nitride and pad oxide layers are removed by wet etching exposing the device areas. A sacrificial oxide layer is formed by thermal oxidation in the device areas and is then removed by wet etching to remove any surface damage. Now, by the method of this invention, the shape of the LOCOS field oxide is modified by depositing a conformal insulating layer, such as silicon oxide (SiO2) deposited by chemical vapor deposition (CVD) on the substrate and over the LOCOS field oxide. The conformal insulating layer is anisotropically plasma etched back to the substrate leaving sidewall portions of the insulating layer on the thinner portions of the LOCOS field oxide, thereby modifying the shape of the field oxide by forming a thicker oxide layer over the bird""s beak. As described later, this thicker oxide modifies the channel-stop implant profile, which increases the threshold voltages and/or reduces leakage currents, which eliminates the need for higher implant doses that are known to cause higher leakage currents. A thin oxide implant layer is formed on the device areas and a patterned photoresist implant mask is used to form P-wells by ion implantation, the channel-stop implant regions under the field oxide by implanting through the modified field oxide having the sidewall portions, and a deep implant to prevent latchup. The thicker field oxide at the perimeter resulting from the sidewall portions modifies the profile of the channel-stop implant in the substrate. This forms a channel-stop implant closer to the field oxide/substrate interface under the bird""s beak, which results in increased threshold voltages and reduced leakage currents. Also, the thicker field oxide further increases the threshold voltage.